元器件交易网www.cecb2b.com SN74CBTLV3257LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999DDDDDDFunctionally Equivalent to QS32575-Ω Switch Connection Between Two PortsIsolation Under Power-Off ConditionsESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)Latch-Up Performance Exceeds 100 mA PerJESD 78, Class IIPackage Options Include Thin VerySmall-Outline (DGV), Small-Outline (D),Shrink Small-Outline (DBQ), and ThinShrink Small-Outline (PW) PackagesD, DBQ, DGV, OR PW PACKAGE(TOP VIEW)S1B11B21A2B12B22AGND12345678161514131211109VCCOE4B14B24A3B13B23AdescriptionThe SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistanceof the switch allows connections to be made with minimal propagation delay.The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when theoutput-enable (OE) input is high.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.The SN74CBTLV3257 is characterized for operation from –40°C to 85°C.FUNCTION TABLEINPUTSOELLHSLHXFUNCTIONA port = B1 portA port = B2 portDisconnectPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Copyright © 1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comSCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999SN74CBTLV3257LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER logic diagram (positive logic)1A4SW21B1 3SW756SW9111B22ASW2B12B23ASW3B1SW12103B24ASW144B1SW134B2S1OE15simplified schematic, each FET switchAB(OE)2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN74CBTLV3257LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 VContinuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mAInput clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mAPackage thermal impedance, θJA (see Note 2):D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/WDBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/WDGV package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/WPW package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CStorage temperature range, Tstg –65†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51.recommended operating conditions (see Note 3)MINVCCVIHVILSupply voltageHighlevelcontrolinputvoltageHigh-level control input voltageLowlevelcontrolinputvoltageLow-level control input voltageVCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 VVCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 V2.31.720.70.8MAX3.6UNITVVVTAOperating free-air temperature–4085°CNOTE 3:All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVIKIIIoffICC∆ICC§CiCiio(OFF)(OFF)Control inputsControl inputsA portB portVCC = 3 V,VCC = 3.6 V,VCC = 0,VCC = 3.6 V,VCC = 3.6 V,VI = 3 V or 0VO = 3 V or 0,3Vor0VCC = 2.3 V,23VTYPatVCC = 2.5 VTYP at V=25Vron¶VCC = 3 VTEST CONDITIONSII = –18 mAVI = VCC or GNDVI or VO= 0 to 4.5 VIO = 0,VI = VCC or GNDOne input at 3 V,Other inputs at VCC or GND3OEVCCOE = VVI = 0=0VI = 1.7 V,VI = 0=0II = 64 mAII = 24 mAII = 15 mAII = 64 mAII = 24 mAII = 15 mA5.510.5552755884077ΩMINTYP‡MAX–1.2±11010300UNITVµAµAµAµApFpFVI = 2.4 V,1015‡All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.§This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.¶Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determinedby the lower of the voltages of the two (A or B) terminals.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999SN74CBTLV3257LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER switching characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figures 1 and 2)PARAMETERFROM(INPUT)A or B†SSSOEOETO(OUTPUT)B or AA or BA or BA or BA or BA or B1.81.711.91VCC = 2.5 V± 0.2 VMINMAX0.356.16.14.85.65.51.81.7121.6VCC = 3.3 V± 0.3 VMINMAX0.255.35.34.555.5nsnsnsnsnsUNITtpdtentdistentdis†The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, whendriven by an ideal voltage source (zero output impedance).PARAMETER MEASUREMENT INFORMATIONVCC = 2.5 V ± 0.2 VS12 × VCCOpenGND500 ΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCGNDFrom OutputUnder TestCL = 30 pF(see Note A)500 ΩLOAD CIRCUITOutputControltPZLVCCOutputWaveform 1S1 at 2 × VCC(see Note B)tPZHVOHOutputWaveform 2S1 at GND(see Note B)VCCVCC/2VCC/20 VtPLZVCCVCC/2VOL + 0.15 VVOLtPHZVCC/2VOHVOH – 0.15 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESInputVCC/2tPLHVCC/20 VtPHLVCC/2VCC/2VOLOutputVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage Waveforms4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN74CBTLV3257LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999PARAMETER MEASUREMENT INFORMATIONVCC = 3.3 V ± 0.3 VFrom OutputUnder TestCL = 50 pF(see Note A)500 ΩS12 × VCCOpenGND500 ΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCGNDLOAD CIRCUITOutputControltPZLVCCOutputWaveform 1S1 at 2 × VCC(see Note B)tPZHVOHOutputWaveform 2S1 at GND(see Note B)VCCVCC/2VCC/20 VtPLZVCCVCC/2VOL + 0.3 VVOLtPHZVCC/2VOHVOH – 0.3 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESInputVCC/2tPLHVCC/20 VtPHLVCC/2VCC/2VOLOutputVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 2. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.com
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